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d a t a sh eet product speci?cation file under integrated circuits, ic12 2000 dec 07 integrated circuits pcf8820 67 101 grey-scale/ecb colour dot matrix lcd driver
2000 dec 07 2 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 contents 1 features 2 applications 3 general description 4 ordering information 5 block diagram 6 pinning 6.1 pad configuration 6.2 pad functions 6.2.1 row driver outputs 6.2.2 column driver outputs 6.2.3 ground supply 6.2.4 supply voltage 6.2.5 voltage multiplier output 6.2.6 voltage multiplier regulation input 6.2.7 supply voltage of bias voltage generator 6.2.8 lcd intermediate bias voltages 6.2.9 serial data input 6.2.10 serial data output 6.2.11 serial clock input 6.2.12 slave address inputs 6.2.13 oscillator signal input 6.2.14 external reset input 6.2.15 test pads 7 functional description 7.1 oscillator 7.2 i 2 c-bus interface controller 7.3 input filters 7.4 display data ram (ddram) 7.5 timing generator 7.6 address counter 7.7 display address counter 7.8 command decoder 7.9 column driver outputs 7.10 row driver outputs 7.11 bias voltage generator 7.12 high voltage generator 7.13 temperature compensation 7.14 temperature sensor 7.15 lcd driver waveforms 7.16 ddram to display mapping 7.17 ddram addressing 7.18 i 2 c-bus interface 7.18.1 bit transfer 7.18.2 start and stop conditions 7.18.3 system configuration 7.18.4 acknowledge 7.18.5 i 2 c-bus protocol 7.18.6 command decoder 7.18.7 display data byte 8 instructions 8.1 description of the bit functions 8.1.1 power-down mode 8.1.2 partial screen mode 8.1.3 y-address of ddram 8.1.4 bias system 8.1.5 high voltage generator configuration 8.1.6 temperature read-out 8.1.7 v lcd control register 8.1.8 grey-scale register and grey-scale level 8.1.9 direct drive mode 8.1.10 frame frequency calibration 8.2 reset and initialization 9 limiting values 10 handling 11 dc characteristics 12 timing 13 application information 13.1 programming example for the pcf8820 13.2 examples of effects on the display 13.3 high voltage generator 13.4 application for cog 13.5 typical system configuration 13.6 external supply of v lcdin 14 bonding pad information 15 device protection circuits 16 tray information 17 data sheet status 18 definitions 19 disclaimers 20 bare die disclaimer 21 purchase of philips i 2 c components
2000 dec 07 3 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 1 features single-chip lcd controller and driver for grey-scale/ electrically controlled birefringence (ecb) colour 4 grey levels/colours (2-bit) definable from 64 levels 67 row and 101 column outputs display data ram 67 101 2-bit with linear ram addressing partial screen mode with reduced current consumption (8 rows at top or bottom of display) on-chip: C generation of lcd supply voltage (v lcdout ); external supply also possible C configurable voltage multiplier factor of 8, 7, 6, 5, 4, 3 or 2; direct drive also possible C selectable linear temperature compensation of v lcdout C generation of intermediate lcd bias voltages C oscillator requires no external components; external clock also possible. temperature read-out fast mode i 2 c-bus interface (400 kbits/s) frame frequency calibration via software software selectable bias configuration compatible with 4-bit, 8-bit or 16-bit microcontrollers multiplex rates of 1 : 67 or 1 : 8 logic supply voltage range from 2.5 to 5.5 v (v dd1 to v ss1 ) high voltage generator supply voltage range from 2.7 to 5.5 v (v dd2 to v ss1 and v dd3 to v ss2 ) bias voltage generator supply voltage range (v lcdin to v ss1 ): C from 7 to 14.5 v at a multiplex rate of 1 : 67 C from 4.5 to 14.5 v in partial screen mode at a multiplex rate of 1 : 8. low power consumption, suitable for battery operated systems slim chip layout, suitable for chip-on-glass applications software selectable top and bottom row swap for adapting driver to different glass-layouts cmos compatible inputs manufactured in silicon gate cmos process. 2 applications mobile telecommunication systems battery powered equipment point of sale terminals instrumentation automotive information systems. 3 general description the pcf8820 is a low power cmos lcd row/column driver, designed to drive grey-scale/ ecb colour dot matrix graphic displays at a multiplex rate of 1 : 67. in the partial screen mode, only 8 rows are driven at a multiplex rate of 1:8. this chip provides all the necessary display functions, including on-chip generation of the lcd supply voltage and lcd bias voltages. consequently, fewer external components are required and the power consumption is low. the pcf8820 interfaces with most microcontrollers and communicates via a two-line bidirectional bus (i 2 c-bus). all inputs are cmos compatible. remark: the waveform generation for ecb colour is identical to that used for grey-scale. 4 ordering information type number package name description version PCF8820U - chip with bumps in tray -
2000 dec 07 4 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 5 block diagram handbook, full pagewidth mgt114 display data ram (ddram) display data latches column drivers c0 to c100 pcf8820 command decoder address counter display address counter timing generator oscillator osc i 2 c-bus interface controller input filters sa1 scl sda_in sda_out v lcdout v lcdsense v lcdin t4 t5 t6 t3 t2 t1 v ss1 v dd1 high voltage generator bias voltage generator temperature sensor r0 to r66 row drivers 26 to 126 165 164 163 v 5 v 4 v 3 v 2 162 3 to 25, 232 to 222, 148 to 127, 151 to 161 166 to 171 172 173 to 178 205 221 212 213 217 218 215, 216 195, 196 res 219 197 214 220 sa0 204 179 to 184 v dd2 188 to 194 v dd3 185 to 187 206 to 211 v ss2 198 to 203 fig.1 block diagram.
2000 dec 07 5 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 6 pinning 6.1 pad con?guration the pad configuration is shown in fig.32. symbol pad description r0 to r22 3 to 25 lcd row driver outputs (block 1) r23 to r33 232 to 222 lcd row driver outputs (block 2) r34 to r55 148 to 127 lcd row driver outputs (block 3) r56 to r66 151 to 161 lcd row driver outputs (block 4) c0 to c100 26 to 126 lcd column driver outputs v ss1 206 to 211 ground supply 1 v ss2 198 to 203 ground supply 2 v dd1 179 to 184 supply voltage 1 of logic v dd2 188 to 194 supply voltage 2 of high voltage generator; temperature read-out v dd3 185 to 187 supply voltage 3 of high voltage generator; temperature read-out v lcdout 173 to 178 voltage multiplier output v lcdsense 172 voltage multiplier regulation input v lcdin 166 to 171 supply voltage for lcd (bias voltage generator) v 2 165 lcd intermediate bias voltage 2; for test purposes only v 3 164 lcd intermediate bias voltage 3; for test purposes only v 4 163 lcd intermediate bias voltage 4; for test purposes only v 5 162 lcd intermediate bias voltage 5; for test purposes only sda_in 195 and 196 serial data input sda_out 197 serial data output (acknowledge) scl 215 and 216 serial clock input sa0 204 i 2 c-bus slave address input 0 (bit 0) sa1 214 i 2 c-bus slave address input 1 (bit 1) osc 220 oscillator signal input res 219 external reset input (active low) t1 205 test 1 input t2 221 test 2 output t3 212 test 3 i/o t4 213 test 4 i/o t5 217 test 5 input t6 218 test 6 output
2000 dec 07 6 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 6.2 pad functions 6.2.1 r ow driver outputs row driver outputs (r0 to r66) are the outputs for the lcd row drive signals. they should be connected directly to the 67 rows of the lcd. if less than 67 rows are required, the unused outputs must be left open-circuit. 6.2.2 c olumn driver outputs column driver outputs (c0 to c100) are the outputs for the lcd column drive signals. they should be connected directly to the 101 columns of the lcd. if less than 101 columns are required, the unused column outputs must be left open-circuit. 6.2.3 g round supply the ground supply rails (v ss1 and v ss2 ) must be connected together. v ss1 is related to v dd1 and v dd3 ; v ss2 is related to v dd2 . 6.2.4 s upply voltage the supply voltage rails (v dd1 ,v dd2 and v dd3 ) must be connected together when the same supply is used for both the logic circuits and for the voltage multiplier. when the circuits are fed separately, v dd2 and v dd3 must be connected to the same supply. 6.2.5 v oltage multiplier output v lcdout is the output of the voltage multiplier of the high voltage generator. 6.2.6 v oltage multiplier regulation input v lcdsense is the regulation input of the high voltage multiplier and must be connected to v lcdout . 6.2.7 s upply voltage of bias voltage generator v lcd is the supply voltage on pad v lcdin for the bias voltage generator which supplies the lcd outputs. the voltage on pad v lcdin must not be lower than v dd1 . if v lcd is generated internally, pad v lcdout must be connected to pad v lcdin . if v lcd is supplied externally, the external supply voltage must be connected to pad v lcdin . an external supply voltage must be applied after applying v dd1 , and it must be removed before or when removing v dd1 (see fig.25). it is recommended that an external supply voltage is applied after leaving the reset state. the external supply voltage can stay applied in the power-down mode. when an external supply voltage is used, pads v lcdin , v lcdsense and v lcdout do not have to be connected together. however, if pads v lcdsense and v lcdout are both connected to pad v lcdin , the current consumption can be reduced under the following conditions: the output of v lcdout is set to high-impedance (see table 8) the high voltage programming range is selected by setting bit prs = 1, the maximum voltage multiplier on factor 8 and the v lcd control register on the maximum value (see table 2). 6.2.8 lcd intermediate bias voltages the lcd intermediate bias voltages (v 2 ,v 3 ,v 4 and v 5 ) which are applied to the lcd columns and rows are present on these pads for test purposes. they must be left open-circuit in the application. 6.2.9 s erial data input sda_in is the serial data input from the i 2 c-bus. 6.2.10 s erial data output sda_out is the serial data output (data, acknowledge) for the i 2 c-bus. connecting pad sda_out to pad sda_in makes the sda line fully i 2 c-bus compatible. not connecting pad sda_in to pad sda_out allows the device to be used in applications in which the acknowledge bit is not required. in chip-on-glass (cog) applications, it is sometimes beneficial not to connect pad sda_out to pad sda_in. this is because in cog applications where the track resistance from pad sda_out to the system sda line is significant, a voltage divider is created by the bus pull-up resistor and the indium tin oxide (ito) track resistance. this divider could prevent the pcf8820 from asserting a valid logic 0 level during an acknowledge cycle. in cog applications, where the acknowledge cycle is required, the track resistance from the pad sda_out to the system sda line must be minimized to guarantee a valid low-level. 6.2.11 s erial clock input scl is the serial clock input from the i 2 c-bus.
2000 dec 07 7 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 6.2.12 s lave address inputs these inputs (sa0 and sa1) allow up to four pcf8820 drivers to be controlled on the same i 2 c-bus. inputs sa0 and sa1 represent respectively bit 0 and bit 1 of the slave address. 6.2.13 o scillator signal input pad osc must be connected directly to v dd1 when the on-chip oscillator is used. no external components are required. it should be noted that any voltage drop of v dd1 may affect the performance of the on-chip oscillator. an external clock must be connected to input osc. 6.2.14 e xternal reset input a low-level on input res initializes the chip. 6.2.15 t est pads the test pads (t1, t2, t3, t4, t5 and t6) must not be accessible to the user. pads t1, t3 and t4 must be connected to v ss1 , pad t5 must be connected to v dd1 , and pads t2 and t6 must be left open-circuit. 7 functional description 7.1 oscillator the on-chip oscillator provides the clock signal for the lcd system. the clock mode is controlled via the i 2 c-bus interface. a clock signal must always be present, except in the power-down mode, to prevent the lcd entering a dc state. 7.2 i 2 c-bus interface controller the i 2 c-bus interface controller receives and executes the commands sent via the i 2 c-bus. the pcf8820 acts as an i 2 c-bus slave receiver/transmitter and therefore it cannot control the bus communication. 7.3 input ?lters rc low-pass filters are provided on inputs sda_in, scl and res to enhance noise immunity in electrically adverse environments. 7.4 display data ram (ddram) the pcf8820 contains a 67 101 2-bit static ram, which stores the display data. the ram comprises 17 banks of 101 bytes (17 101 8 bits). not all of the last bank is implemented. during ram access, data is transferred to the ram via the i 2 c-bus interface controller. 7.5 timing generator the timing generator produces the various signals required to drive the internal circuitry. internal chip operation is not affected by operations on the i 2 c-bus. 7.6 address counter the address counter generates write addresses to the ddram. during a write operation, display data is stored at the addressed locations. 7.7 display address counter the display address counter generates read addresses to the ddram. during a read operation, display data is read out to the lcd. 7.8 command decoder the command decoder receives command words which are followed by data byte(s) from the i 2 c-bus. the command decoder identifies the command words and determines the destination for the data byte(s). 7.9 column driver outputs the lcd driver section has 101 outputs (c0 to c100) which should be connected directly to the column drive inputs of the lcd. the column driver signals are generated in accordance with the multiplexed row signals and with the data in the display data latch. the programmed grey-scale levels are built-up in the lcd over four frames (n1 1 ,n1 2 ,n1 3 and n1 4 ) as shown in figs 3, 4 and 5. 7.10 row driver outputs the lcd driver section has 67 outputs (r0 to r66) which should be connected directly to the row drive inputs of the lcd. the row driver signals are generated in accordance with the selected lcd drive mode.
2000 dec 07 8 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 7.11 bias voltage generator the bias voltage generator generates 4 buffered intermediate lcd bias voltages. it contains 4 operational amplifiers and an input reference voltage generator. it can operate in two voltage ranges: normal mode (from 7.0 to 14.5 v) partial screen mode (from 4.5 to 14.5 v). 7.12 high voltage generator the high voltage generator contains a voltage multiplier which uses a charge pump circuit supplied by v dd2 and v dd3 . the multiplier is software programmable with a factor from 2 to 8. in the direct drive mode the output voltage v lcdout =v dd2 . 7.13 temperature compensation the viscosity of the liquid crystal depends on the temperature; so to maintain optimum contrast at lower temperatures v lcd needs usually to be increased. fig.2 shows v lcd as a function of the temperature for a typical high multiplex rate liquid crystal. linear temperature compensation is supported in the pcf8820. the temperature coefficient for v lcdout can be set to one of 8 values by setting bits tc 2 to tc 0 . 7.14 temperature sensor the pcf8820 has a built-in temperature sensor. the sensor monitors the temperature and writes an 8-bit number into the status register. the temperature sensor and status register can both be accessed via the i 2 c-bus interface controller. the temperature sensor allows any temperature compensation to be implemented; any programmable parameter can be optimized as a function of the sensor read-out temperature. 7.15 lcd driver waveforms the lcd waveforms are shown in figs 3, 4 and 5. at frame inversion, the pcf8820 generates a dummy row cycle, where no row is selected. this ensures equal conditions for the first row after frame inversion as for the other rows. therefore the effective multiplex rate in all modes is 1 : (multiplex rate + 1). 7.16 ddram to display mapping ddram to display mapping is shown in fig.6. handbook, halfpage mgt123 v lcd (v) t amb ( c) 0 (1) (2) fig.2 lcd supply voltage as a function of the temperature. (1) lcd characteristic. (2) linear temperature compensation.
2000 dec 07 9 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... o ok, full pagewidth mgt115 v lcd v 2 v 3 v 4 v 5 v ss row 0 r0(t) v lcd v 2 v 3 v 4 v 5 v ss row 1 r1(t) v lcd v 2 v 3 v 4 v 5 v ss col 0 c0(t) v lcd v 2 v 3 v 4 v 5 v ss col 1 c1(t) state1 state2 4 79 16 x x 88 16 x x 88 16 x x 79 16 x x 79 16 x x 4 5 4 4 n1 1 n1 2 n1 3 n1 4 n2 1 frame 0012 660012 660012 660012 660012 66 v lcd v 3 v 3 - v 2 v lcd - v 2 0 v v state1 (t) v lcd v 3 v 3 - v 2 v lcd - v 2 0 v v state2 (t) - v lcd v 4 - v lcd v 4 - v 5 - v 5 0 v - v lcd v 4 - v lcd v 4 - v 5 - v 5 0 v o ok, full pagewidth mgt115 v lcd v 2 v 3 v 4 v 5 v ss row 0 r0(t) v lcd v 2 v 3 v 4 v 5 v ss row 1 r1(t) v lcd v 2 v 3 v 4 v 5 v ss col 0 c0(t) v lcd v 2 v 3 v 4 v 5 v ss col 1 c1(t) state1 state2 4 79 16 x x 88 16 x x 88 16 x x 79 16 x x 79 16 x x 4 5 4 4 n1 1 n1 2 n1 3 n1 4 n2 1 frame 0012 660012 660012 660012 660012 66 v lcd v 3 v 3 - v 2 v lcd - v 2 0 v v state1 (t) v lcd v 3 v 3 - v 2 v lcd - v 2 0 v v state2 (t) - v lcd v 4 - v lcd v 4 - v 5 - v 5 0 v - v lcd v 4 - v lcd v 4 - v 5 - v 5 0 v fig.3 typical lcd driver waveforms at a multiplex rate of 1 : 67. example for setting grey-scale register. row0, col0: gs = 17 row1, col0: gs = 0 row0, col1: gs = 30 row1, col0: gs = 63 (63 will be set to 64; see section 8.1.8). v state1 (t) = c1(t) - r0(t) v state2 (t) = c1(t) - r1(t)
2000 dec 07 10 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... o ok, full pagewidth mgt116 v lcd v 2 v 3 v 4 v 5 v ss row 0 r0(t) v lcd v 2 v 3 v 4 v 5 v ss row 1 r1(t) v lcd v 2 v 3 v 4 v 5 v ss col 0 c0(t) v lcd v 2 v 3 v 4 v 5 v ss col 1 c1(t) state1 state2 4 79 16 x x 88 16 x x 88 16 x x 79 16 x x 79 16 x x 4 5 4 4 n1 1 n1 2 n1 3 n1 4 n2 1 frame 0012 70012 70012 7 0012 70012 7 v lcd v 3 v 3 - v 2 v lcd - v 2 0 v v state1 (t) v lcd v 3 v 3 - v 2 v lcd - v 2 0 v v state2 (t) - v lcd v 4 - v lcd v 4 - v 5 - v 5 0 v - v lcd v 4 - v lcd v 4 - v 5 - v 5 0 v fig.4 typical lcd driver waveforms at a multiplex rate of 1 : 8 for partial screen mode. example for setting grey-scale register. row0, col0: gs = 17 row1, col0: gs = 0 row0, col1: gs = 30 row1, col0: gs = 63 (63 will be set to 64; see section 8.1.8). v state1 (t) = c1(t) - r0(t) v state2 (t) = c1(t) - r1(t)
2000 dec 07 11 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... o ok, full pagewidth mgt117 state1 state2 n1 1 n1 2 n1 3 n1 4 n2 1 frame 0012 70012 70012 7 0012 70012 7 v lcd 0.5v lcd 0.5v lcd 0.5v lcd 0.5v lcd - 0.5v lcd - 0.5v lcd v ss row 0 r0(t) v lcd v ss row 1 r1(t) 0 v v lcd - v lcd v state2 (t) 0 v v lcd - v lcd v state1 (t) v lcd v ss col 0 c0(t) v lcd v ss col 1 c1(t) fig.5 typical lcd driver waveforms at a multiplex rate of 1 : 8, for partial screen mode and bias system 1 / 2 . v state1 (t) = c1(t) - r0(t). v state2 (t) = c1(t) - r1(t). example for setting grey-scale register. row0, col0: gs = 0 row1, col0: gs = 63 (63 will be set to 64; see section 8.1.8). row0, col1: gs = 63 (63 will be set to 64; see section 8.1.8). row1, col0: gs = 63 (63 will be set to 64; see section 8.1.8).
2000 dec 07 12 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 mgt118 handbook, full pagewidth db7 db6 db5 db4 db3 db2 db1 db0 p3 msb p2 lsb p2 msb p1 lsb p1 msb p0 lsb p0 msb p3 lsb msb lsb bank 0 bank 2 bank 16 top of lcd lcd r0 r8 r16 r56 r52 bank 15 bank 14 bank 1 bank 3 r4 r12 r60 lsb msb pixel 0 p0 p1 p2 p3 p0 p1 p2 p3 bank 13 . . . . . . . . r64 x x r66 r = row p = pixel fig.6 ddram to display mapping.
2000 dec 07 13 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 7.17 ddram addressing data is written in 8-bit bytes into the display data ram matrix of the pcf8820 (see figs 6 to 8). the display data ram comprises a matrix of 67 101 2 bits. the columns are addressed by the address pointer. the address ranges are: x = 0 to 100 (64h) and y=0to16 (10h). it should be noted that only 3 rows are addressed in bank 16. addresses outside these ranges are not allowed. bit mx (see table 3) enables or disables horizontal address space mirroring: when bit mx = 0, mirroring is disabled. the address corresponds to col0 (see fig.7). when bit mx = 1, mirroring is enabled and address x = 0 corresponds to col0 (see fig.8). bit mx determines how data is written to the ram. if bit mx is changed after writing data to the ram, no change on the display will be visible. handbook, full pagewidth mgt119 0 100 x address col0 lsb msb 0 16 y address fig.7 ram x-address format for mirroring disabled. handbook, full pagewidth mgt120 x address col0 lsb msb 0 16 y address 100 0 fig.8 ram x-address format for mirroring enabled.
2000 dec 07 14 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 bit v (see table 3) selects either horizontal or vertical address mode: in vertical address mode (bit v = 1), the y-address is incremented after each byte (see fig.9). after y = 16, the y-address sequence returns to y = 0 and the x-address is incremented to address the next column. in horizontal address mode (bit v = 0) the x-address is incremented after each byte (see fig.10). after x = 100, the x-address sequence returns to x = 0 and the y-address is incremented to address the next row. after the very last address (x = 100 and y = 16), the address pointers return to the first address (x = 0 and y = 0). it should be noted that in bank 16 only bits db0 to db5 of the data will be written into the ram. handbook, full pagewidth mgt121 017 118 219 320 13 14 15 16 0 16 1716 0 100 x address y address fig.9 writing data to ram sequence in vertical address mode. handbook, full pagewidth mgt122 012345 100 201 101 102 202 203 303 304 404 1414 1515 1616 0 16 1716 0 100 x address y address fig.10 writing data to ram sequence in horizontal address mode.
2000 dec 07 15 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 7.18 i 2 c-bus interface the i 2 c-bus allows bidirectional data communication between different ics or modules. the serial data input line and serial data output line are connected together, so representing the serial data (sda) line. see section 13.4 for layout considerations. the sda line and the serial clock line (scl) line must be connected to a positive supply voltage via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 7.18.1 b it transfer one data bit is transferred during a clock pulse period. the data on the sda line must remain stable during the high period of the clock pulse, otherwise any change in the data within this period will be interpreted as a control signal (see fig.11). 7.18.2 start and stop conditions both data and clock lines are high when the bus is not busy (see fig.12). a start condition (s) occurs when the data line goes from high-to-low while the clock is high. a stop condition (p) occurs when the data line goes from low-to-high while the clock is high. handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl fig.11 bit transfer. handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition fig.12 definition of start and stop conditions.
2000 dec 07 16 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 7.18.3 s ystem configuration thd system components are defined below (see fig.13): transmitter: the device which sends data to the bus receiver: the device which receives data from the bus master: the device which initiates a transfer, generates clock signals and terminates a transfer slave: the device addressed by a master multi-master: more than one master can attempt to control the bus at the same time without corrupting the message arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted synchronization: procedure to synchronize the clock signals of two or more devices. 7.18.4 a cknowledge each 8-bit data byte transferred over the bus must be followed by an acknowledge bit (see fig.14). during the acknowledge clock pulse a high-level signal is put on the bus by the transmitter. a slave receiver which is addressed must generate an acknowledge bit after the reception of each data byte. a master receiver must generate an acknowledge bit after receiving a data byte that has been clocked out of the slave transmitter. the device that acknowledges must pull-down the sda line to a low-level during the acknowledge clock pulse. set-up and hold times must be taken into consideration to ensure that the sda line is stable during the high period of the acknowledge related clock pulse. a master receiver must signal an end-of-data to the slave transmitter by not generating an acknowledge bit on the last byte that has been clocked out of the slave transmitter. in this event the slave transmitter must leave the data line high to allow the master to generate a stop condition. for the pcf8820 the acknowledge bit is output at pad sda_out. mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig.13 system configuration. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master fig.14 acknowledgement on the i 2 c-bus.
2000 dec 07 17 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 7.18.5 i 2 c- bus protocol the pcf8820 is a slave transmitter/receiver. if data is to be read from the device, the sda_out output must be used. before any data is transferred over the i 2 c-bus, the destination device is addressed first (see fig.15). the pcf8820 has four 7-bit slave addresses reserved: 0111 100, 0111 101, 0111 110 and 0111 111. the two least significant bits of the slave address are set by connecting slave address inputs sa1 and sa0 to either v ss1 (logic 0) or v dd1 (logic 1). a write sequence (see fig.17) is initiated with a start condition (s) from the i 2 c-bus master which is followed by the slave address. only the addressed slave acknowledges. after acknowledgement, one or more command words follow which define the status of the addressed slave. a command word consists of a control byte (see fig.16) defining continuation bit co and register selection bit rs, plus a data byte. the last control byte is indicated by resetting bit co = 0. the control and data bytes are also acknowledged by all addressed slaves on the bus. depending on the setting of bit rs in the last control byte, either a series of display data bytes or command data bytes may follow. if bit rs = 1, the data bytes are stored as display data in the ddram at the address specified by the data pointer. the data pointer is automatically incremented. if bit rs = 0, the data byte is interpreted as a command byte to be decoded and the device will be set according to the received commands. only the addressed pcf8820 acknowledges after each byte is received. the i 2 c-bus master issues a stop condition (p) at the end of the transmission. mgu185 s01111 sa0 sa1 a slave address r/w acknowledge bit start condition slave address bit 1 read/write bit slave address bit 0 fig.15 slave address. mgt124 corsxxxxxx control byte register selection bit continuation bit fig.16 control byte. handbook, full pagewidth mgt125 s01111 s a 0 s a 1 0a acknowledgement from pcf8820 acknowledgement from pcf8820 acknowledgement from pcf8820 acknowledgement from pcf8820 acknowledgement from pcf8820 1 control byte a data byte data byte m 3 0 bytes 1 byte slave address 2n 3 0 bytes a co update data pointer co 0a ap rs r/w control byte rs fig.17 write sequence: master transmits bytes to slave receiver.
2000 dec 07 18 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 for a read sequence (see fig.18), the addressed pcf8820 will immediately start to output the requested data until a not acknowledge is transmitted by the master. before the read access, the user has to set bit rs to the appropriate value by a preceding write access. the sequence should be terminated by a stop condition when no further access is required, or by a re-start condition if further access is required. 7.18.6 c ommand decoder the command decoder identifies command words received via the i 2 c-bus. bit 7 of the control byte is named bit co (see fig.16): bit co = 1 indicates that only one command byte or ddram data byte will follow next bit co = 0 indicates that a stream of command bytes or ddram data bytes will follow next depending on last status of bit rs. bit 6 of a control byte is named bit rs: bit rs = 1 indicates that another ddram data byte will follow next bit rs = 0 indicates that another command byte will follow next. the definition of bits co and rs is shown in table 1. 7.18.7 d isplay data byte a display data byte for grey-scale is shown in fig.19. mgt126 s01111 s a 0 1a acknowledgement from pcf8820 not acknowledgement from master temperature readout value ap s a 1 slave address r/w stop condition fig.18 read sequence: master receives bytes from slave transmitter status register. mgt127 p3 lsb pixel 3 pixel 2 pixel 1 pixel 0 p3 msb p2 lsb p2 msb p1 lsb p1 msb p0 lsb p0 msb db7 db6 db5 db4 db3 db2 db1 db0 msb lsb fig.19 grey-scale display data byte. table 1 de?nition of bits co and rs bit value action co 0 last control byte to be sent; only a stream of data bytes are allowed to follow; this stream may only be terminated by a stop or re-start condition 1 another control byte will follow the data byte unless a stop or re-start condition is received rs 0 data byte will be decoded and used to set up the device data byte will return the sensor temperature read-out 1 data byte will be stored in the ddram ram read-back (not supported)
2000 dec 07 19 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 8 instructions the pcf8820 interfaces via the i 2 c-bus. the clock of the lcd is not required to process instructions. the data received by the pcf8820 is either instruction data which defines its operating mode or display data to be stored in its ddram. the type of data is identified by bit rs. when bit rs = 0, the pcf8820 will respond to the instructions. when bit rs = 1, the pcf8820 will load the data into its ddram. there are four types of instruction data whose functions are listed below: define pcf8820 functions, such as display configuration, etc. set ddram addresses perform data transfers to ddram other functions. in normal use, the most frequently used instructions are those which perform data transfers to the ddram. address pointer update follows after the data byte has been written to the dram. this reduces the program load of the microcontroller. undefined register locations are not allowed. the instruction set comprises several command pages. a command page is selected by setting bits h 0 to h 2 . the instruction set is given in table 2. the bit functions are described in detail in section 8.1. table 2 instruction set instruction control bits (1) command byte description rs r/ w db7 db6 db5 db4 db3 db2 db1 db0 independent command page (h 2 = x, h 1 = x, h 0 = x); note 2 write data 1 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 writes data to ddram read temperature 01tr 7 tr 6 tr 5 tr 4 tr 3 tr 2 tr 1 tr 0 reads sensor temperature read-out nop 000000000 0no operation default h 2 to h 0 000000000 1 jumps to function and ram command page function and ram command page (h 2 = 0, h 1 = 0, h 0 =0) instruction set 0000001h 2 h 1 h 0 selects a command page select function 000001dopdv 0 data order; power-down control; address mode set y address of ddram 00010y 4 y 3 y 2 y 1 y 0 selects y-address of ddram: 0 y 16 set x address of ddram 001x 6 x 5 x 4 x 3 x 2 x 1 x 0 selects x-address of ddram: 0 x 100 display setting command page (h 2 = 0, h 1 = 0, h 0 =1) display control 00000001d e selects display mode external display control 0000001mxmyps mirror x; mirror y; partial screen mode bias system 0000010bs 2 bs 1 bs 0 selects bias system bias system 1 / 2 000011100bs 1 / 2 set bias system 1 / 2 for partial screen mode
2000 dec 07 20 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 notes 1. bit r/ w is set in the slave address byte; bit rs is set in the control byte. 2. x = dont care. display part 0001000dp 2 dp 1 dp 0 set display for partial screen mode hvgen command page (h 2 = 0, h 1 = 1, h 0 =0) high voltage generator control 00000001prshve set v lcdout programming range and high voltage generator on high voltage generator con?guration 0000001s 2 s 1 s 0 set voltage multiplier factor temperature control 0000010tc 2 tc 1 tc 0 set temperature coef?cient temperature measurement control 000010000sm start temperature measurement v lcd control 0 0 1 v op6 v op5 v op4 v op3 v op2 v op1 v op0 set v lcd register value: 0 v op 127 grey-scale/colour command page (h 2 = 0, h 1 = 1, h 0 =1) grey-scale register control 00010000gr 1 gr 0 select grey-scale register: 0 gr 3 grey-scale level control 0010gs 5 gs 4 gs 3 gs 2 gs 1 gs 0 set grey-scale register value: 0 gs 63 special feature command page (h 2 = 1, h 1 = 0, h 0 =0) display off, direct drive mode 00000001dofdm display off; voltage multiplier in direct drive mode oscillator setting 00000010ecoc select external clock; start oscillator calibration row block swapping 00010trsbrs00 0 top row swap; bottom row swap instruction control bits (1) command byte description rs r/ w db7 db6 db5 db4 db3 db2 db1 db0
2000 dec 07 21 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 8.1 description of the bit functions table 3 instruction set bit functions bit reset state value function d 7 to d 0 -- data to be written to ddram tr 7 to tr 0 -- read-out value of sensor temperature h 2 to h 0 command page numbers 000 000 function and ram 001 display setting 010 high voltage generator setting 011 grey-scale/colour 100 special features do data order when written to ddram 0 0 normal (see fig.6) 1 swapped: db7 <-> db0, db6 <-> db1, etc. pd operation mode 0 operating mode 1 1 power-down mode; see section 8.1.1 v address mode 0 0 horizontal address mode: data is written to ddram (see fig.10) 1 vertical address mode: data is written to ddram (see fig.9) y 4 to y 0 0 - y-address of the ddram points to the rows; the address range is from 0 to 16 (10h); see section 8.1.3 x 6 to x 0 0 - x-address of the ddram points to the columns; the address range is from 0 to 100 (64h) d, e display mode 00 00 display blank: using the value in grey-scale register 0 01 all display segments on: using the value in grey-scale register 3 10 normal mode: using the values of the four grey-scale registers appropriate to the ram data 11 inverse video: using the values in all four grey-scale registers as in normal mode but with their values swapped (gs 0 and gs 3 values transposed, gs 1 and gs 2 values transposed) mx horizontal address space mirroring; see figs 7 and 8; see table 10 0 0 disabled: data to ddram is written from left (x = 0) to right (x = 100) 1 enabled: data to ddram is written from right (x = 0) to left (x = 100) my vertical address space mirroring; see table 10 0 0 disabled: normal display 1 enabled: data is immediately mirrored vertically on the lcd. the status of bit my takes effect when data is read from the ddram and when generating column signals.
2000 dec 07 22 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 ps screen mode 0 0 full display mode: multiplex rate is 1 : 67 1 partial screen mode: multiplex rate is 1 : 8; see section 8.1.2. bs 2 , bs 1 , bs 0 000 - bias system selection bits; see section 8.1.4 bs 1 / 2 bias system selection 0 0 setting of bits bs2 to bs0 1 bias system 1 / 2 ; see section 8.1.4 dp 2 , dp 1 , dp 0 display part 000 000 ddram bank 0 to 1: first 8 rows 111 ddram bank 14 to 15: last 8 rows prs v lcdout programming range; see fig.20 0 0 low range 1 high range hve high voltage generator 0 0 disabled 1 enabled s 2 , s 1 , s 0 voltage multiplier factor; see section 8.1.5 000 000 2 v dd2 001 3 v dd2 010 4 v dd2 011 5 v dd2 100 6 v dd2 101 7 v dd2 110 8 v dd2 tc 2 , tc 1 , tc 0 temperature coef?cient; see chapter 11 000 000 coefficient 0 001 coefficient 1 010 coefficient 2 011 coefficient 3 100 coefficient 4 101 coefficient 5 110 coefficient 6 111 coefficient 7 sm temperature measurement 0 0 no measurement 1 start measurement v op6 to v op0 0 - v lcd control register bits; see section 8.1.7 bit reset state value function
2000 dec 07 23 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 gr 1 , gr 0 grey-scale register selection: 00 00 register 0: applied if ddram content is 00 01 register 1: applied if ddram content is 01 10 register 2: applied if ddram content is 10 11 register 3: applied if ddram content is 11 gs 5 to gs 0 0- grey-scale level bits; in the reset state all 4 grey-scale registers are reset to 0; see section 8.1.8 dof display on/off 0 display on 1 1 display off: the state of the pcf8820 is equivalent to power-down mode (bit pd = 1). however, temperature measurement is still possible dm drive of voltage multiplier 0 0 no direct drive 1 direct drive: v lcdout =v dd2 ; see section 8.1.9 ec clock selection 0 internal clock 1 external clock oc oscillator setting; see section 8.1.10 0 0 stop calibration of frame frequency 1 start calibration of frame frequency trs top rows 0 0 not swapped 1 swapped: the signals for row driver outputs r23 to r33 appear at outputs r56 to r66, and the signals for row driver outputs r56 to r66 appear at outputs r23 to r33 brs bottom rows 0 0 not swapped 1 swapped: the signals for row driver outputs r0 to r22 appear at outputs r34 to r55, and the signals for row driver outputs r34 to r55 appear at outputs r0 to r22 bit reset state value function
2000 dec 07 24 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 8.1.1 p ower - down mode during power-down (bit pd = 1) all static currents are switched off (no internal oscillator, no timing, no lcd segment drive system) and all lcd outputs are internally connected to v ss . to decrease the voltage at v lcdout very fast the following features can be used: select the direct drive mode by setting bit dm = 1 resulting in v lcdout =v dd2 select the non direct drive mode by setting bit dm = 0, resulting in v lcdout = 0 v (output high-impedance). during power-down: all lcd outputs at v ss (display off) oscillator is off intermediate bias voltage generator is off high voltage generator is disabled; however, the status of bit hve is unchanged (see table 8) an external v lcd can be disconnected from v lcdin the i 2 c-bus is operational; commands can be executed ddram contents is not cleared; ddram data can be written register settings remain unchanged temperature measurement is not possible. 8.1.2 p artial screen mode partial screen mode allows data to be displayed of ddram bank 0 to 1 on the first 8 rows or bank 14 to 15 on the last 8 rows, depending on the status of bits dp 2 to dp 0 . if bit my = 0, data is displayed either on rows 0 to 7 (first 8 rows) or on rows 56 to 63 (last 8 rows). if bit my = 1, data is displayed either on rows 66 to 59 (first 8 rows) or on rows 10 to 3 (last 8 rows). the partial screen mode also allows v lcdin to be reduced to save power. frame frequency calibration is not allowed in the partial screen mode. 8.1.3 y- address of ddram bits y 4 to y 0 define the y-address of the ddram. table 4 y-address 8.1.4 b ias system different lcd bias voltage settings are required at different multiplex rates. the status of bits bs 2 to bs 0 and bit bs 1 / 2 select different bias systems which determine the intermediate bias voltage levels between v lcdin and v ss1 . it should be noted that the bias system selected by bit bs 1 / 2 is independent of the bias systems selected by bits bs 2 to bs 0 . a value n attributed to each bias system is used to calculate these levels (see table 5). the optimum value for n is given by: where m is the multiplex rate. table 6 shows how bias voltage levels are calculated for three of the available bias systems using supported n values. y 4 y 3 y 2 y 1 y 0 ram bank 00000 bank 0 00001 bank 1 00010 bank 2 00011 bank 3 00100 bank 4 00101 bank 5 00110 bank 6 00111 bank 7 01000 bank 8 01001 bank 9 01010 bank 10 01011 bank 11 01100 bank 12 01101 bank 13 01110 bank 14 01111 bank 15 10000 bank 16 nm3 C =
2000 dec 07 25 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 table 5 programming the required bias system table 6 examples of lcd bias voltages bs2 bs1 bs0 bs 1 / 2 n bias system comment 00007 1 / 11 00106 1 / 10 01005 1 / 9 recommended at multiplex rate 1 : 67 01104 1 / 8 10003 1 / 7 10102 1 / 6 11001 1 / 5 11100 1 / 4 recommended at multiplex rate 1 : 8 xxx1 - 2 1 / 2 allows a lower v lcdin at multiplex rate 1 : 8 bias voltage level on pad calculating bias voltage bias system 1 / 9 (n = 5) 1 / 4 (n = 0) 1 / 2 (n = - 2) v lcdout v lcdin v lcdin v lcdin v lcdin v 2 8 / 9 v lcdin 3 / 4 v lcdin 1 / 2 v lcdin v 3 7 / 9 v lcdin 1 / 2 v lcdin v ss1 v 4 2 / 9 v lcdin 1 / 2 v lcdin v lcdin v 5 1 / 9 v lcdin 1 / 4 v lcdin 1 / 2 v lcdin v ss1 v ss1 v ss1 v ss1 v ss1 n3 + n4 + ------------ - v lcdin n2 + n4 + ------------ - v lcdin 2 n4 + ------------ - v lcdin 1 n4 + ------------ - v lcdin 8.1.5 h igh voltage generator configuration the pcf8820 incorporates a software configurable voltage multiplier which uses a charge pump circuit supplied by v dd2 and v dd3 . after a reset the voltage multiplier factor is set to 2 (v lcdout =2 v dd2 ). other voltage multiplier factors are set by bits s 2 to s 0 . to reduce high current peaks at voltage multiplier start-up, it is recommended that the voltage multiplier is switched on using the following procedure: 1. set bit dm = 1 and bit pd = 1 2. set multiplication factor to 2 by setting bits s 2 to s 0 to logic 0 3. set register value v op to the desired value, bit prs = 1 and bit hve = 1 4. set bit pd = 0, which switches on the charge pump (at multiplication factor 2) 5. increment the multiplication factor to the desired value for v lcdout using bits s 2 to s 0 . 8.1.6 t emperature read - out the pcf8820 has a built-in temperature sensor. at the end of a temperature measurement, the sensor writes a temperature value to the status register. the temperature value is an 8-bit number represented by bits tr 7 to tr 0 in the status register which can be read via the i 2 c-bus. to save power, the sensor need only be enabled when a measurement is required. a measurement is initialized by setting bit sm = 1 which will be automatically cleared after 5 clock cycles (from internal oscillator or external clock). the internal oscillator will be initialized and allowed to warm-up for approximately 2 frame periods, after which a measurement will be initiated at the start of the next frame and completing after 2 frames.
2000 dec 07 26 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 it is not possible to measure temperature in power-down mode. during a temperature measurement, the status register value remains zero until the measurement has completed and then the register is updated with the current temperature value (non-zero value). because the i 2 c-bus interface is asynchronous to the temperature measurement, the value read from the status register should be validated by reading the status register a few times. during a temperature measurement, the temperature coefficient (tc) has to be selected. the ideal temperature read-out can be calculated by the equation: where t is the on-chip temperature in c and a is the conversion constant (see chapter 11). to improve the accuracy of the temperature measurement, it is recommended that the temperature read-out is calibrated during the products final assembly. calibration of the temperature read-out requires a measurement to be made at a defined ideal temperature. the offset between the ideal temperature value and the measured temperature value is calculated by: tr offset =tr ideal - tr meas where tr meas is the actual temperature read-out of the pcf8820. the offset value must be stored in a non-volatile register, such as an eeprom. a calibrated temperature read-out can be calculated for each measurement by the equation: tr cal =tr meas +tr offset the accuracy after the calibration is 10% 1 bit of the difference between the measured temperature and the calibration temperature. for this reason, it is recommended that a calibration is performed at or near the most sensitive lcd temperature. for example: calibration temperature is 25 c and the measured temperature is - 20 c. the relative error a= 0.10 {25 - ( - 20)} 1 bit a a= 4.5 1.13 a= 5.63 c. this calibration accuracy is valid for temperature measurements made when the supply voltage value is the same as when it was calibrated. 8.1.7 v lcd control register the v lcdout value can be set by software using the bits v op6 to v op0 of the v lcd control register. the programmed value for v lcd has to be calculated for a reference temperature, called the cut-point temperature t cp , using the equation: v lcd (at t cp )=a+b v op the values for parameters t cp , a and b are given in table 7, and their relationship with the v lcd control register values are shown in fig.20. the v lcdout generated is dependent on the operating temperature t oper , the selected temperature coefficient tc and the programmed value for v lcd at the reference temperature t cp and is calculated by the equation: v lcd (at t oper )=v lcd (at t cp ) {1 + tc (t oper - t cp )} two overlapping v lcd ranges are selectable by bit prs (see table 7 and fig.20). the maximum voltage that can be generated depends on the values of v dd2 and v dd3 , and the display load current. at a multiplex rate of 1 : 67, the optimum operating voltage for the lcd can be calculated by the equation: where v th is the threshold voltage of the liquid crystal material used. the practical value for v lcd is determined by equating v off(rms) with the defined lcd threshold voltage (v th ), which is the typically value when the lcd exhibits approximately 10% contrast. table 7 parameter values for programming v lcd control register tr ideal 128 t 27 c C () + 1 a -- - = symbol value unit bit prs = 0 bit prs = 1 t cp 23.0 23.0 c a 4.500 10.215 v b 0.045 0.045 v programming range 4.5 to 10.215 10.215 to 15.93 v v lcd 1671 + + 21 1 67 1 + -------------------- C ? ?? ------------------------------------------------ - v th 6.975 @ v th =
2000 dec 07 27 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 handbook, full pagewidth mgt128 00 01 02 a v lcd (v) 03 04 05 06 . . . 7d 7e 7f 00 01 02 03 04 05 06 . . . 7d 7e 7f register value b low (1) high (2) fig.20 generated v lcdout set by programming v lcd control register value (bits v op6 to v op0 ). (1) bit prs = 0: v lcd programming range is low. (2) bit prs = 1: v lcd programming range is high. the programming range for the generated v lcdout allows values above the maximum value of v lcd . therefore, the user must ensure that the v lcd control register value and the temperature coefficient selected, will never allow the maximum v lcd limit to be exceeded for all conditions and including all tolerances. the customer must also ensure that the v lcd control register value will never be lower than v dd1 or v dd2 , except in the power-down mode, for all conditions and including all tolerances. 8.1.8 g rey - scale register and grey - scale level the pcf8820 has 4 grey-scale registers selected by bits gr 0 and gr 1 , which define the four grey intensity levels. each of the 4 registers contain 6 bits allowing to select one out of the 64 grey levels. a grey-scale register must be addressed before it can be written to by using the instruction grey-scale register (see table 2). the content of the grey-scale register (bits gs 5 to gs 0 ) is set by the instruction grey-scale level control (see table 2). it should be noted that a grey-scale register setting of 63 is internally converted to 64. even numbers are preferred; odd numbers produce a small dc component in the waveform of the respective column (see fig.3). the grey-scale level for each pixel is effected by writing the resultant grey-scale register value into the ddram (see fig.6). one of the grey-scale registers can be used to create a blinking cursor. the intensity of the pixels comprising the cursor are to be defined by the value in the grey-scale register. the brightness/colour of the cursor pixels can be changed by selecting a different grey-scale register containing a different grey-scale value. a blinking cursor can be effected by continuously switching the content of one grey-scale register between the two grey-scales from e.g. white to black and back again with a frequency of 2 hz giving the impression of a blinking cursor. this procedure causes less load for the microcontroller than changing all pixels which form the desired cursor. this implies the display has 3 grey-scale levels left e.g. off, grey and on.
2000 dec 07 28 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 8.1.9 d irect drive mode the voltage multiplier is in the direct drive mode (v lcdout =v dd2 ) in the following settings (see table 8): if bit dm = 1 and power-down mode (bit pd = 1) if bit dm = 1 and display off mode (bit dof = 1) if bit dm = 1 and high voltage generator is disabled (bit hve = 0). it is recommended to always select the direct drive mode before switching on the voltage multiplier. this is a feature which can be used to reduce v lcdout very quickly, or to avoid high current when the voltage multiplier starts up. output v lcdout is high-impedance when bit dm = 0 and bit pd = 1, bit dm = 0 and bit dof = 0 or when bit dm = 0, bit pd = 0 and bit hve = 0. table 8 output v lcdout as a function of bits dm, hve, pd and dof; note 1 note 1. x = dont care. 8.1.10 f rame frequency calibration the pcf8820 uses on-chip software to calibrate the frame frequency. after reset, the frame frequency calibration is disabled (bit oc = 0). frame frequency calibration can only be performed if the pcf8820 is not in power-down mode or in the partial screen mode. the calibration is initiated by setting bit oc = 1 and is stopped by setting bit oc = 0. the time between calibration start and stop must be 190 m s to give a frame frequency of 77 hz (typical value). all other commands are allowed during a calibration. the frame frequency calibration uses a pre-divider which has a range from 1 : 1 to 1 : 15. the default ratio after reset is 1 : 4. the calibration period determines the pre-divider ratio for the oscillator frequency or external clock signal. the resulting frame frequency is calculated by the equation: where f clk can be either the internal oscillator clock signal or an external clock signal source. figure 21 shows the resulting frame frequency at different clock frequencies and at different pre-divider ratios, for a calibration period of 190 m s. the frame frequency calibration can also be used to set the frame frequency to a lower than typical value with a corresponding reduction in current consumption. the necessary calibration period (time between calibration start and stop) can be estimated by the equation: where t cal is the calibration time in m s and f frame is the desired frame frequency in hz. figure 22 shows the resulting frame frequency as a function of the calibration period at different pre-divider ratios at a clock frequency of 336 khz. 8.2 reset and initialization after power-on the content of all internal registers including the ddram are in an undefined state. a reset pulse must be applied within a specified time to reset all internal registers. a reset can be achieved by applying an external reset pulse (active low) to pad res. when reset occurs within the specified time all internal registers are reset, however the ddram is still undefined. after v dd1 has reached its minimum value, the res input level must be 0.3v dd1 after a maximum time t su (see fig.24). after reset the state of the pcf8820 is as follows: default values of bits and registers as seen in table 3 all row and column outputs are at v ss (display off) v lcdout is high-impedance ram data is undefined. dm hve pd dof v lcdout 0 x 1 x high z 0 x x 1 high z 0 0 0 0 high z 1000v dd2 1x1xv dd2 1xx1v dd2 x 1 0 0 internally generated v lcd f frame f clk 1088 ------------- pre-divider ratio hz [] = t cal 77 (hz) 190 m s () f frame ------------------------------------------------- =
2000 dec 07 29 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 handbook, full pagewidth 750 100 f clk (khz) f frame (hz) 60 150 200 1:2 1:3 1:4 1:5 1:6 1:7 1:8 250 300 350 550 400 600 450 650 500 700 mgt129 80 85 90 70 95 75 65 fig.21 calibrated frame frequency as a function of clock frequency and pre-divider ratio. t cal = 190 m s. handbook, full pagewidth 800 110 t cal ( m s) f frame (hz) 10 100 150 200 250 300 350 550 400 600 450 650 500 750 700 mgt130 50 60 70 80 30 90 100 40 20 1:4 1:8 1:11 1:12 1:3 1:5 1:6 1:7 1:9 1:10 1:13 1:14 1:15 fig.22 frame frequency as a function of the calibration time and pre-divider ratio. f clk = 336 khz.
2000 dec 07 30 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 9 limiting values in accordance with the absolute maximum rating system (iec 60134); note 1. note 1. all voltages are referred to v ss = 0 v. stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. parameters are valid over operating temperature range unless otherwise speci?ed. 10 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, it is good practice to take normal precautions appropriate to handling mos devices (see handling mos devices ). 11 characteristics v dd1 = 2.5 to 5.5 v; v dd2 =v dd3 = 2.7 to 5.5 v; v ss1 =v ss2 =0v;v lcdin = 4.5 to 14.5 v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter min. max. unit v dd supply voltage - 0.5 +6.5 v v lcdin supply voltage for the lcd - 0.5 +15 v v n voltage on v any v lcd related pin - 0.5 v lcdin + 0.5 v any other pin - 0.5 v dd1 + 0.5 v i i dc input current - 10 +10 ma i o dc output current - 10 +10 ma i ss ground supply current - 50 +50 ma p tot total power dissipation - 100 mw p/out power dissipation per output - 10 mw t amb ambient temperature - 40 +85 c t stg storage temperature - 65 +150 c t j junction temperature - 150 c symbol parameter conditions min. typ. max. unit supplies v dd1 supply voltage 1 of logic circuits 2.5 - 5.5 v v dd2 supply voltage 2 of voltage multiplier 2.7 - 5.5 v v dd3 supply voltage 3 of voltage multiplier 2.7 - 5.5 v v lcdin supply voltage of lcd graphic mode 7.0 - 14.5 v partial screen mode; note 1 v dd - 14.5 v
2000 dec 07 31 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 i dd(tot) total supply current into pins v dd1 , v dd2 and v dd3 power-down mode; v lcdin = 8.6 v (external); notes 2 and 3 - 0.5 10 m a partial screen mode; v lcdin = 4.5 v (external); note 3 - 15 35 m a partial screen mode; v lcdin = 4.5 v (internal); lcd load is 10 m a; voltage multiplier factor 3; bias system = 1 / 6 ; notes 3 and 4 - 210 300 m a normal mode; v lcdin = 8.6 v (external); note 3 - 20 35 m a normal mode; v lcdin = 8.6 v (internal); lcd load is 10 m a; voltage multiplier factor 5; bias system = 1 / 9 ; notes 3 and 4 - 430 680 m a i lcdin supply current of v lcdin power-down mode; v lcdin = 8.6 v (external); bias system = 1 / 9 ; v lcd control value = 28h; bit prs = 1; notes 3 and 5 - 615 m a partial screen mode; v lcdin = 4.5 v (external); lcd load is 10 m a; bias system = 1 / 6 ; v lcd control value = 00h; bit prs = 0; notes 3, 4 and 5 - 45 70 m a normal mode; v lcdin = 8.6 v (external); lcd load is 10 m a; bias system = 1 / 9 ; v lcd control value = 5ch; bit prs = 0; notes 3, 4 and 5 - 60 95 m a symbol parameter conditions min. typ. max. unit
2000 dec 07 32 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 logic inputs p ads sa0, sa1, res, t1, t3, t4 and t5 v il low-level input voltage v ss1 - 0.3v dd1 v v ih high-level input voltage 0.7v dd1 - v dd1 v i l leakage current v i =v dd1 or v ss1 - 1 - +1 m a p ad osc v i low-level input voltage v ss1 - v ss1 + 0.1 v v i high-level input voltage v dd1 - 0.1 - v dd1 v i l leakage current v i =v dd1 or v ss1 - 1 - +1 m a i 2 c-bus p ads sda_in and scl v il low-level input voltage v ss1 - 0.3v dd1 v v ih high-level input voltage 0.7v dd1 - 5.5 v i l leakage current v i =v dd1 or v ss1 - 1 - +1 m a p ad sda_out i ol low-level output current v ol = 0.4 v; v dd1 = 5 v 3.0 -- ma i l leakage current v i =v dd1 or v ss1 - 1 - +1 m a column and row outputs r col column output resistance c0 to c100 v dd1 =5v; v lcdin =12v; i l = 100 m a; outputs tested one at a time -- 10 k w r row row output resistance r0 to r66 v dd1 =5v; v lcdin =12v; i l = 100 m a; outputs tested one at a time -- 3.0 k w v bias(col) bias voltage tolerance c0 to c100 - 100 0 +100 mv v bias(row) bias voltage tolerance r0 to r66 - 100 0 +100 mv lcd supply voltage generator s tability d v lcdout tolerance of internally generated v lcdout t amb = - 20 to +85 c; v lcdout 12 v -- 4.6 % t emperature coefficient of v lcdout ;t amb = - 20 to +85 c tc 0 temperature coef?cient 0 -- 0.04 10 - 3 - k - 1 tc 1 temperature coef?cient 1 -- 1.89 10 - 3 - k - 1 tc 2 temperature coef?cient 2 -- 2.05 10 - 3 - k - 1 tc 3 temperature coef?cient 3 -- 2.22 10 - 3 - k - 1 tc 4 temperature coef?cient 4 -- 2.38 10 - 3 - k - 1 symbol parameter conditions min. typ. max. unit
2000 dec 07 33 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 notes 1. the minimum value for v lcdin is limited by the supply voltages v dd1 and v dd2 : a) for v dd1 4.5 v and v dd2 4.5 v: v lcdin > 4.5 v. b) for v dd1 > 4.5 v or v dd2 > 4.5 v: v lcdin > highest value of v dd1 or v dd2 . 2. all static currents are switched off in power-down mode; no external clock. 3. v dd1 =v dd2 =v dd3 = 2.75 v; lcd outputs are open-circuit; inputs connected to v dd1 or v ss1 ; i 2 c-bus inactive; external clock with f ext = 336 khz; t amb =27 c. 4. the typical currents are measured on a sample base with the ddram and grey-scale registers loaded with data which would produce the display shown in fig.23 if an lcd was connected. extensive use of grey-scales will increase current consumption compared to black and white mode. if specified, the maximum current is tested with a regular pattern which is equivalent in current to the display shown in fig.23. 5. voltage multiplier disabled; pins v lcdin , v lcdout and v lcdsense connected together. tc 5 temperature coef?cient 5 -- 2.55 10 - 3 - k - 1 tc 6 temperature coef?cient 6 -- 2.72 10 - 3 - k - 1 tc 7 temperature coef?cient 7 -- 2.98 10 - 3 - k - 1 r eference temperature t cp cut-point temperature - 23 - c temperature read-out a conversion constant - 1.13 - c/bit a tol tolerance of a same supply voltage v dd -- 10 % repeatability -- 1 bit affect of changing v dd -- 0.5 bit/v symbol parameter conditions min. typ. max. unit handbook, full pagewidth mgt131 fig.23 display used to define ddram and grey-scales for current measurements.
2000 dec 07 34 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 12 timing v dd1 = 2.5 to 5.5 v; v dd2 =v dd3 = 2.7 to 5.5 v; v ss1 =v ss2 =0v; v lcdin = 4.5 to 14.5 v; t amb = - 40 c to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit clock signal f frame lcd frame frequency not calibrated; note 1 44 77 158 hz f frame(cal1) lcd frame frequency calibrated; accurate calibration timing of 190 m s; note 2 68 77 91 hz f frame(cal2) lcd frame frequency calibrated; accurate calibration timing of 190 m s 63 77 96 hz f osc oscillator frequency not calibrated; note 3 190 336 670 khz p ad osc f ext external clock frequency not calibrated 190 336 670 khz reset timing; see fig.24 p ad res t wl reset pulse width low 1.0 --m s t wh reset pulse width high 1.5 --m s t w(spike) tolerable spike width on res input -- 10 ns t su reset-low pulse set-up time after power-on v dd = 2.75 v; note 4 -- 30 m s t oper end of reset to interface being operational -- 3 m s lcd on and off timing; see fig.25 p ad v lcdin t lcd(on) external lcd turn-on time after v dd1 turns on 1 -- ms t lcd(off) external lcd turn-off time before v dd1 turns off 1 -- ms i 2 c-bus timing; see fig.26; note 5 p ads scl and sda f scl scl clock frequency 0 - 400 khz t low scl low time 1.3 --m s t high scl high time 0.6 --m s t su;dat data set-up time 100 -- ns t hd;dat data hold time 0 - 0.9 m s t r rise time sda and scl note 6 20 + 0.1 c b - 300 ns t f fall time sda and scl note 6 20 + 0.1 c b - 300 ns c b capacitive load represented by each bus line -- 400 pf t su;sta set-up time repeated start 0.6 --m s t hd;sta hold time start condition 0.6 --m s
2000 dec 07 35 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 notes 1. frame frequency: or 2. v dd unchanged after frequency calibration. 3. not available at any pad. 4. decoupling capacitor between v lcdin and v ss1 is 100 nf. a higher capacitance increases t su and a higher v dd1 , v dd2 or v dd3 reduces t su . 5. all timing values are valid within v dd1 ,v dd2 ,v dd3 and t amb ranges and are referenced to v il and v ih with an input voltage swing from v ss1 to v dd1 . 6. c b is the total capacitance (in pf) of one bus line. t su;sto set-up time for stop condition 0.6 --m s t w(spike) tolerable spike width on bus -- 50 ns t buf bus free time 1.3 --m s symbol parameter conditions min. typ. max. unit f frame f ext 4352 ------------ - = f frame f osc 4352 ------------ - = handbook, full pagewidth mgt135 t su t wh t wh t wl t wl t wl t wl t oper v dd1 res v dd1 res sda, scl res fig.24 reset timing.
2000 dec 07 36 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 handbook, full pagewidth mgt136 t lcd(on) v dd1 v lcdin t lcd(off) fig.25 timing diagram of applying and removing the external lcd supply voltage to and from pad v lcdin . o ok, full pagewidth sda mga728 sda scl t su;sta t su;sto t hd;sta t buf t low t hd;dat t high t r t f t su;dat fig.26 i 2 c-bus timing.
2000 dec 07 37 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 13 application information 13.1 programming example for the pcf8820 it should be noted that only a part of the lcd is shown in the lcd column of table 9. table 9 programming example step serial bus byte lcd operation db7 db6 db5 db4 db3 db2 db1 db0 1 01111sa1sa00 start slave address, r/ w=0 2 10000000 control byte: co = 1, rs = 0 3 00000001 h 2 to h 0 independent command: select function and ram command page (h 2 to h 0 = 000) 4 10000000 control byte: co = 1, rs = 0 5 00001001 function and ram command page: select display setting command page (h 2 to h 0 = 001) 6 10000000 control byte: co = 1, rs = 0 7 00000110 display setting command page: set normal display mode (d = 1, e = 0) 8 10000000 control byte: co = 1, rs = 0 9 00010010 display setting command page: set bias system = 1 / 9 (bs 2 to bs 0 = 010) 10 10000000 control byte: co = 1, rs = 0 11 01000000 display setting command page: select ?rst 8 rows for partial screen mode (dp 2 to dp 0 = 000) 12 10000000 control byte: co = 1, rs = 0 13 00000001 h 2 to h 0 independent command: select function and ram command page (h 2 to h 0 = 000) 14 10000000 control byte: co = 1, rs = 0 15 00010110 function and ram command page: select power-down mode (pd = 1) and vertical address mode (v = 1) 16 10000000 control byte: co = 1, rs = 0 17 00001100 function and ram command page: select special feature command page (h 2 to h 0 = 100) 18 10000000 control byte: co = 1, rs = 0 19 00000101 special feature command page: enable display (dof = 0) and enable direct drive (dm = 1) to pre-charge the charge pump 20 10000000 control byte: co = 1, rs = 0
2000 dec 07 38 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 21 00000001 h 2 to h 0 independent command: select function and ram command page (h 2 to h 0 = 000) 22 10000000 control byte: co = 1, rs = 0 23 00001010 function and ram command page: select hvgen command page (h 2 to h 0 = 010) 24 10000000 control byte: co = 1, rs = 0 25 00001000 hv gen command page: select voltage multiplier factor 2 (s 2 to s 0 = 000) 26 10000000 control byte: co = 1, rs = 0 27 00010010 hv gen command page: select temperature coef?cient 2 (tc 2 to tc 0 = 010) 28 10000000 control byte: co = 1, rs = 0 29 00000100 hv gen command page: select low v lcd programming range (prs = 0), hvgen off (hve = 0) 30 10000000 control byte: co = 1, rs = 0 31 11011011 hv gen command page: set v lcd to 8.595 v (v op6 to v op0 = 1011011) 32 10000000 control byte: co = 1, rs = 0 33 00000001 h 2 to h 0 independent command: select function and ram command page (h 2 to h 0 = 000) 34 10000000 control byte: co = 1, rs = 0 35 00001011 function and ram command page: select grey-scale/colour command page (h 2 to h 0 = 011) 36 10000000 control byte: co = 1, rs = 0 37 01000000 gre y-scale/colour command page: select grey-scale register 0 (gr 1 to gr 0 = 00) 38 10000000 control byte: co = 1, rs = 0 39 10000000 gre y-scale/colour command page: set grey-scale to 0 (gs 5 to gs 0 = 000000) 40 10000000 control byte: co = 1, rs = 0 41 01000001 gre y-scale/colour command page: select grey-scale register 1 (gr 1 to gr 0 = 01) 42 10000000 control byte: co = 1, rs = 0 step serial bus byte lcd operation db7 db6 db5 db4 db3 db2 db1 db0
2000 dec 07 39 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 43 10010100 gre y-scale/colour command page: set grey-scale to 20 (gs 5 to gs 0 = 010100) 44 10000000 control byte: co = 1, rs = 0 45 01000010 gre y-scale/colour command page: select grey-scale register 2 (gr 1 to gr 0 = 10) 46 10000000 control byte: co = 1, rs = 0 47 10101000 gre y-scale/colour command page: set grey-scale register 2 to 40 (gs 5 to gs 0 = 101000) 48 10000000 control byte: co = 1, rs = 0 49 01000011 gre y-scale/colour command page: select grey-scale register 3 (gr 1 to gr 0 = 11) 50 10000000 control byte: co = 1, rs = 0 51 10111111 gre y-scale/colour command page: set grey-scale register 3 to 63 (gs 5 to gs 0 = 111111) 52 10000000 control byte: co = 1, rs = 0 53 00000001 h 2 to h 0 independent command: select function and ram command page (h 2 to h 0 = 000) 54 10000000 control byte: co = 1, rs = 0 55 00001010 function and ram command page: select hvgen command page (h 2 to h 0 = 010) 56 10000000 control byte: co = 1, rs = 0 57 00000101 hv gen command page: enable hvgen (hve = 1) and select low v lcd programming range (prs = 0) 58 10000000 control byte: co = 1, rs = 0 59 00000001 h 2 to h 0 independent command: select function and ram command page (h 2 to h 0 = 000) 60 10000000 control byte: co = 1, rs = 0 61 00010010 function and ram command page: select normal operation (pd = 0) and vertical address mode (v = 1) 62 10000000 control byte: co = 1, rs = 0 63 00001010 function and ram command page: select hvgen command page (h 2 to h 0 = 010) step serial bus byte lcd operation db7 db6 db5 db4 db3 db2 db1 db0
2000 dec 07 40 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 64 10000000 control byte: co = 1, rs = 0 65 00001001 hv gen command page: select voltage multiplier factor 3 (s 2 to s 0 = 001, incremented to 3x) 66 10000000 control byte: co = 1, rs = 0 67 00001010 hv gen command page: select voltage multiplier factor 4 (s 2 to s 0 = 010) 68 10000000 control byte: co = 1, rs = 0 69 00001011 hv gen command page: select voltage multiplier factor 5 (s 2 to s 0 = 011, incremented to 5x) 70 01000000 control byte: co = 0, rs = 1 71 11111111 data write column 0 (vertical addressing): address x and y are initialized to 0 by default, so they are not set here 72 00000011 data write: next write to subsequent rows ?lling up column 0 with 00h 73to 8900000000no display change data writes (17 bytes) 90 00110011 data write column 1 (vertical addressing) 91 00000000 data write 92 to 108 00000000no display change data writes (17 bytes) 109 00111111 data write column 2 (vertical addressing) 110 00000000 data write 111 to 127 00000000no display change data writes (17 bytes) step serial bus byte lcd operation db7 db6 db5 db4 db3 db2 db1 db0 mgt143 mgt144 mgt145 mgt145 mgt146 mgt146
2000 dec 07 41 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 128 00000000 data write column 3 (vertical addressing) 129 00000000 data write 130 to 146 00000000no display change data writes (17 bytes) 147 11111111 data write column 4 (vertical addressing) 148 00000011 data write 149 to 165 00000000no display change data writes (17 bytes) 166 00110000 data write column 5 (vertical addressing) 167 00000000 data write 168 to 184 00000000no display change data writes (17 bytes) 185 11111111 data write column 6 (vertical addressing) 186 00000011 data write: last data; stop transmission 187 01111sa1sa00no display change restart, slave address, r/ w=0 188 10000000no display change control byte: co = 1, rs = 0 189 00000001no display change h 2 to h 0 independent command: select function and ram command page (h 2 to h 0 = 000) step serial bus byte lcd operation db7 db6 db5 db4 db3 db2 db1 db0 mgt146 mgt146 mgt147 mgt148 mgt149 mgt149 mgt150 mgt151
2000 dec 07 42 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 190 10000000no display change control byte: co = 1, rs = 0 191 00001001no display change function and ram command page: select display setting command page (h 2 to h 0 = 001) 192 10000000no display change control byte: co = 1, rs = 0 193 00000111 display mode: set inverse video mode (d = 1, e = 1) 194 10000000no display change control byte: co = 1, rs = 0 195 00000001no display change h 2 to h 0 independent command: select function and ram command page (h 2 to h 0 = 000) 196 10000000no display change control byte: co = 1, rs = 0 197 10000000no display change set x address of ram to 0000000 198 10000000no display change control byte: co = 1, rs = 0 199 01000000no display change set y address of ram to 00000 200 01000000no display change control byte: co = 0, rs = 1 201 01010101 data write column 1 (vertical addressing mode) 202 00000001 data write: last data; stop transmission step serial bus byte lcd operation db7 db6 db5 db4 db3 db2 db1 db0 mgt152 mgt153 mgt154
2000 dec 07 43 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 13.2 examples of effects on the display table 10 examples showing the effects on the lcd of setting bits ps, dp 2 to dp 0 , mx and my example ps dp 2 dp 1 dp 0 mx my display description 1 0 x x x 0 0 normal display 2 0 x x x 1 0 x mirrored only 3 0 x x x 0 1 y mirrored only 4 0 x x x 1 1 x and y mirrored 5 1 0 0 0 0 0 partial screen mode only; ?rst 8 rows selected 6 1 0 0 0 1 0 partial screen mode; x mirrored; ?rst 8 rows selected 7 1 0 0 0 0 1 partial screen mode; y mirrored; ?rst 8 rows selected 8 1 0 0 0 1 1 partial screen mode; x and y mirrored; ?rst 8 rows selected 9 1 1 1 1 0 0 partial screen mode; last 8 rows selected mgt155 mgt156 mgt157 mgt158 mgt159 mgt160 mgt161 mgt162 mgt163
2000 dec 07 44 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 10 1 1 1 1 1 0 partial screen mode; x mirrored; last 8 rows selected 11 1 1 1 1 0 1 partial screen mode; y mirrored; last 8 rows selected 12 1 1 1 1 1 1 partial screen mode; x and y mirrored; last 8 rows selected example ps dp 2 dp 1 dp 0 mx my display description mgt164 mgt165 mgt166
2000 dec 07 45 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 13.3 high voltage generator the high voltage generator contains a voltage multiplier which uses a charge pump circuit supplied by v dd2 and v dd3 . the multiplier is software programmable with a factor from 2 to 8. in the direct drive mode the output voltage v lcdout =v dd2 . when the charge pump is used the total supply current of the pcf8820 at a supply voltage of 3, 4 and 5 v is shown in figs 27, 28 and 29. the separate graphs are shown for each voltage multiplier factor with the following conditions: at t amb v dd1 , v dd2 and v dd3 connected to the same power supply supply line resistors of 50 w (typical value) internal clock not calibrated no lcd connected to the pcf8820 all pixels defined at grey-scale level 32; this is the worst case bias system 1 9 full screen mode (bit ps = 0) at a multiplex rate of 1 : 67 normal display mode. the characteristics shown for each voltage multiplier factor are terminated before v lcdout has been reached the maximum value to indicate that the voltage cannot be increased any further. if a higher voltage is required, a higher voltage multiplier factor must be selected. connecting a lcd may increase the current into pad v lcdin which may affect the current taken by the charge pump and also its efficiency. the amount of current load may depend on the type of lcd used. it is advisable to evaluate the pcf8820 connected to the desired lcd and set to the required mode(s) to produce characteristics similar to figs 27, 28 and 29. the customer can then use these graphs to select the most efficient and safe voltage multiplier factor for each mode required. handbook, full pagewidth 16 1.2 programmed v lcdout (v) i dd(tot) (ma) 0 45678 12 913 10 14 11 15 mgt132 0.8 0.4 1.0 0.6 0.2 x 8 x 2 x 3 x 4 x 5 x 7 x 6 fig.27 charge pump characteristics for v dd =3v.
2000 dec 07 46 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 handbook, full pagewidth 16 1.0 0 45678 12 913 10 14 11 15 mgt133 0.8 0.4 0.6 0.2 x 5 x 8 x 2 x 3 x 4 x 6 x 7 programmed v lcdout (v) i dd(tot) (ma) fig.28 charge pump characteristics for v dd =4v. handbook, full pagewidth 16 1.0 0 45678 12 913 10 14 11 15 mgt134 0.8 0.4 0.6 0.2 x 8 x 7 x 6 x 3 x 2 x 5 x 4 programmed v lcdout (v) i dd(tot) (ma) fig.29 charge pump characteristics for v dd =5v.
2000 dec 07 47 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 13.4 application for cog the pcf8820 physical pad positions are optimized for single plane wiring e.g. for chip-on-glass (cog) display modules (see fig.30). the pad lines are as follows: 3 input/output lines: sda, scl and res 101 column driver lines 33 and 34 row driver lines pads sa0, sa1 and osc can be tied in the application to appropriate levels. for cog applications, it is recommended that the indium tin oxide (ito) track resistance is minimized for the i/o and power supply connections. these connections should have an optimum track resistance of <50 w for the power supply connections and <100 w for the i/o connections. increasing the track resistance reduces the performance and increases the current consumption. the common supply resistor values especially, have to be minimized (<5 w for high supply voltage v p1 , v lcd and gnd). the minimum value required for the external capacitors is: c ext1 > 470 nf (c ext1 >c ext2 recommended) c ext2 > 100 nf (470 nf to 1 m f recommended). a higher value of the capacitors is recommended to reduce the ripple voltage. handbook, full pagewidth mgt137 3 lcd (67 101 pixels) v p1 i/o gnd c ext1 c ext2 r supply r common r i/o v lcd pcf8820 101 colum drivers scl sda_in res v dd1 v dd2 v dd3 v ss1 v lcdin v lcdsense v lcdout v ss2 34 row drivers 33 row drivers fig.30 application diagram for cog display module.
2000 dec 07 48 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 13.5 typical system con?guration the pcf8820 is a low power lcd driver designed to interface with microcontrollers and a wide variety of lcds. the host microcontroller and the pcf8820 are both connected to the i 2 c-bus. the sda and scl lines must be connected to the positive power supply via pull-up resistors. the internal oscillator requires no external components. the appropriate intermediate biasing voltage for the multiplexed lcd waveforms are generated on-chip. the only other connections required to complete the system are the power supplies (v dd1 ,v dd2 and v dd3 ) and ground supplies (v ss1 and v ss2 ), lcd supply (v lcdin ) and system reset ( res), including suitable capacitors for decoupling. 13.6 external supply of v lcdin if an external lcd supply voltage is used, it must be connected to pad v lcdin . if pads v lcdout ,v lcdsense and v lcdin are connected together, the impedance of pad v lcdout should be set high-impedance by setting the status of bits shown in table 8. to obtain the highest resistance and the lowest current into pad v lcdsense ,itis recommended to set the v lcd programming range to high (bit prs = 1) and the v lcd control register value to 127 (maximum value) with bits v op6 to v op0 . it should be noted that v lcdin is not allowed to be lower than v dd1 . an external v lcd must be applied after applying v dd1 , and it must be turned off before (or when) v dd1 is turned off (see fig.25). it is recommended that the external v lcd is applied after leaving the reset state. the external v lcd can stay turned on in power-down mode. handbook, full pagewidth mgt138 host microcontroller lcd panel sda_in v ss2 v ss1 v dd1 v lcdin v lcdout v dd2 v lcdsense v dd3 osc v lcd v p1 v p2 5.5 v scl sda scl sa0 sa1 pcf8820 sda_out r pu r pu res res 101 column drivers 67 row drivers i 2 c-bus fig.31 typical system configuration.
2000 dec 07 49 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 14 bonding pad information symbol pad coordinates (1) xy dummy 1 - 5443.7 - 1162.5 dummy 2 - 5373.7 - 1162.5 row 0 3 - 5233.7 - 1162.5 row 1 4 - 5163.7 - 1162.5 row 2 5 - 5093.7 - 1162.5 row 3 6 - 5023.7 - 1162.5 row 4 7 - 4953.7 - 1162.5 row 5 8 - 4883.7 - 1162.5 row 6 9 - 4813.7 - 1162.5 row 7 10 - 4743.7 - 1162.5 row 8 11 - 4673.7 - 1162.5 row 9 12 - 4603.7 - 1162.5 row 10 13 - 4533.7 - 1162.5 row 11 14 - 4463.7 - 1162.5 row 12 15 - 4393.7 - 1162.5 row 13 16 - 4323.7 - 1162.5 row 14 17 - 4253.7 - 1162.5 row 15 18 - 4183.7 - 1162.5 row 16 19 - 4113.7 - 1162.5 row 17 20 - 4043.7 - 1162.5 row 18 21 - 3973.7 - 1162.5 row 19 22 - 3903.7 - 1162.5 row 20 23 - 3833.7 - 1162.5 row 21 24 - 3763.7 - 1162.5 row 22 25 - 3693.7 - 1162.5 col 0 26 - 3483.7 - 1162.5 col 1 27 - 3413.7 - 1162.5 col 2 28 - 3343.7 - 1162.5 col 3 29 - 3273.7 - 1162.5 col 4 30 - 3203.7 - 1162.5 col 5 31 - 3133.7 - 1162.5 col 6 32 - 3063.7 - 1162.5 col 7 33 - 2993.7 - 1162.5 col 8 34 - 2923.7 - 1162.5 col 9 35 - 2853.7 - 1162.5 col 10 36 - 2783.7 - 1162.5 col 11 37 - 2713.7 - 1162.5 col 12 38 - 2643.7 - 1162.5 col 13 39 - 2573.7 - 1162.5 col 14 40 - 2503.7 - 1162.5 col 15 41 - 2433.7 - 1162.5 col 16 42 - 2363.7 - 1162.5 col 17 43 - 2293.7 - 1162.5 col 18 44 - 2223.7 - 1162.5 col 19 45 - 2153.7 - 1162.5 col 20 46 - 2083.7 - 1162.5 col 21 47 - 2013.7 - 1162.5 col 22 48 - 1943.7 - 1162.5 col 23 49 - 1873.7 - 1162.5 col 24 50 - 1803.7 - 1162.5 col 25 51 - 1663.7 - 1162.5 col 26 52 - 1593.7 - 1162.5 col 27 53 - 1523.7 - 1162.5 col 28 54 - 1453.7 - 1162.5 col 29 55 - 1383.7 - 1162.5 col 30 56 - 1313.7 - 1162.5 col 31 57 - 1243.7 - 1162.5 col 32 58 - 1173.7 - 1162.5 col 33 59 - 1103.7 - 1162.5 col 34 60 - 1033.7 - 1162.5 col 35 61 - 963.7 - 1162.5 col 36 62 - 893.7 - 1162.5 col 37 63 - 823.7 - 1162.5 col 38 64 - 753.7 - 1162.5 col 39 65 - 683.7 - 1162.5 col 40 66 - 613.7 - 1162.5 col 41 67 - 543.7 - 1162.5 col 42 68 - 473.7 - 1162.5 col 43 69 - 403.7 - 1162.5 col 44 70 - 333.7 - 1162.5 col 45 71 - 263.7 - 1162.5 col 46 72 - 193.7 - 1162.5 col 47 73 - 123.7 - 1162.5 col 48 74 - 53.7 - 1162.5 col 49 75 +16.3 - 1162.5 col 50 76 +156.3 - 1162.5 col 51 77 +226.3 - 1162.5 symbol pad coordinates (1) xy
2000 dec 07 50 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 col 52 78 +296.3 - 1162.5 col 53 79 +366.3 - 1162.5 col 54 80 +436.3 - 1162.5 col 55 81 +506.3 - 1162.5 col 56 82 +576.3 - 1162.5 col 57 83 +646.3 - 1162.5 col 58 84 +716.3 - 1162.5 col 59 85 +786.3 - 1162.5 col 60 86 +856.3 - 1162.5 col 61 87 +926.3 - 1162.5 col 62 88 +996.3 - 1162.5 col 63 89 +1066.3 - 1162.5 col 64 90 +1136.3 - 1162.5 col 65 91 +1206.3 - 1162.5 col 66 92 +1276.3 - 1162.5 col 67 93 +1346.3 - 1162.5 col 68 94 +1416.3 - 1162.5 col 69 95 +1486.3 - 1162.5 col 70 96 +1556.3 - 1162.5 col 71 97 +1626.3 - 1162.5 col 72 98 +1696.3 - 1162.5 col 73 99 +1766.3 - 1162.5 col 74 100 +1836.3 - 1162.5 col 75 101 +1976.3 - 1162.5 col 76 102 +2046.3 - 1162.5 col 77 103 +2116.3 - 1162.5 col 78 104 +2186.3 - 1162.5 col 79 105 +2256.3 - 1162.5 col 80 106 +2326.3 - 1162.5 col 81 107 +2396.3 - 1162.5 col 82 108 +2466.3 - 1162.5 col 83 109 +2536.3 - 1162.5 col 84 110 +2606.3 - 1162.5 col 85 111 +2676.3 - 1162.5 col 86 112 +2746.3 - 1162.5 col 87 113 +2816.3 - 1162.5 col 88 114 +2886.3 - 1162.5 col 89 115 +2956.3 - 1162.5 col 90 116 +3026.3 - 1162.5 symbol pad coordinates (1) xy col 91 117 +3096.3 - 1162.5 col 92 118 +3166.3 - 1162.5 col 93 119 +3236.3 - 1162.5 col 94 120 +3306.3 - 1162.5 col 95 121 +3376.3 - 1162.5 col 96 122 +3446.3 - 1162.5 col 97 123 +3516.3 - 1162.5 col 98 124 +3586.3 - 1162.5 col 99 125 +3656.3 - 1162.5 col 100 126 +3726.3 - 1162.5 row 55 127 +3866.3 - 1162.5 row 54 128 +3936.3 - 1162.5 row 53 129 +4006.3 - 1162.5 row 52 130 +4076.3 - 1162.5 row 51 131 +4146.3 - 1162.5 row 50 132 +4216.3 - 1162.5 row 49 133 +4286.3 - 1162.5 row 48 134 +4356.3 - 1162.5 row 47 135 +4426.3 - 1162.5 row 46 136 +4496.3 - 1162.5 row 45 137 +4566.3 - 1162.5 row 44 138 +4636.3 - 1162.5 row 43 139 +4706.3 - 1162.5 row 42 140 +4776.3 - 1162.5 row 41 141 +4846.3 - 1162.5 row 40 142 +4916.3 - 1162.5 row 39 143 +4986.3 - 1162.5 row 38 144 +5056.3 - 1162.5 row 37 145 +5126.3 - 1162.5 row 36 146 +5196.3 - 1162.5 row 35 147 +5266.3 - 1162.5 row 34 148 +5336.3 - 1162.5 dummy 149 +5476.3 - 1162.5 dummy 150 +5581.3 +1162.5 row 56 151 +5301.3 +1162.5 row 57 152 +5231.3 +1162.5 row 58 153 +5161.3 +1162.5 row 59 154 +5091.3 +1162.5 row 60 155 +5021.3 +1162.5 symbol pad coordinates (1) xy
2000 dec 07 51 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 row 61 156 +4951.3 +1162.5 row 62 157 +4881.3 +1162.5 row 63 158 +4811.3 +1162.5 row 64 159 +4741.3 +1162.5 row 65 160 +4671.3 +1162.5 row 66 161 +4601.3 +1162.5 v 5 162 +4421 +1162.5 v 4 163 +4261 +1162.5 v 3 164 +4101 +1162.5 v 2 165 +3941 +1162.5 v lcdin 166 +3806.3 +1162.5 v lcdin 167 +3726.3 +1162.5 v lcdin 168 +3646.3 +1162.5 v lcdin 169 +3566.3 +1162.5 v lcdin 170 +3486.3 +1162.5 v lcdin 171 +3406.3 +1162.5 v lcdsense 172 +3326.3 +1162.5 v lcdout 173 +3246.3 +1162.5 v lcdout 174 +3166.3 +1162.5 v lcdout 175 +3086.3 +1162.5 v lcdout 176 +3006.3 +1162.5 v lcdout 177 +2926.3 +1162.5 v lcdout 178 +2846.3 +1162.5 v dd1 179 +2451.3 +1162.5 v dd1 180 +2371.3 +1162.5 v dd1 181 +2291.3 +1162.5 v dd1 182 +2211.3 +1162.5 v dd1 183 +2131.3 +1162.5 v dd1 184 +2051.3 +1162.5 v dd3 185 +1921.3 +1162.5 v dd3 186 +1841.3 +1162.5 v dd3 187 +1761.3 +1162.5 v dd2 188 +1681.3 +1162.5 v dd2 189 +1601.3 +1162.5 v dd2 190 +1521.3 +1162.5 v dd2 191 +1441.3 +1162.5 v dd2 192 +1361.3 +1162.5 v dd2 193 +1281.3 +1162.5 v dd2 194 +1201.3 +1162.5 symbol pad coordinates (1) xy sda_in 195 +573.3 +1162.5 sda_in 196 +493.3 +1162.5 sda_out 197 +65.9 +1162.5 v ss2 198 - 233.7 +1162.5 v ss2 199 - 313.7 +1162.5 v ss2 200 - 393.7 +1162.5 v ss2 201 - 473.7 +1162.5 v ss2 202 - 553.7 +1162.5 v ss2 203 - 633.7 +1162.5 sa0 204 - 833.7 +1162.5 t1 205 - 1033.7 +1162.5 v ss1 206 - 1113.7 +1162.5 v ss1 207 - 1193.7 +1162.5 v ss1 208 - 1273.7 +1162.5 v ss1 209 - 1353.7 +1162.5 v ss1 210 - 1433.7 +1162.5 v ss1 211 - 1513.7 +1162.5 t3 212 - 1713.7 +1162.5 t4 213 - 1913.7 +1162.5 sa1 214 - 2113.7 +1162.5 scl 215 - 2355 +1162.5 scl 216 - 2435 +1162.5 t5 217 - 2958 +1162.5 t6 218 - 3158.7 +1162.5 res 219 - 3454.7 +1162.5 osc 220 - 4158.7 +1162.5 t2 221 - 4282.7 +1162.5 row 33 222 - 4498.7 +1162.5 row 32 223 - 4568.7 +1162.5 row 31 224 - 4638.7 +1162.5 row 30 225 - 4708.7 +1162.5 row 29 226 - 4778.7 +1162.5 row 28 227 - 4848.7 +1162.5 row 27 228 - 4918.7 +1162.5 row 26 229 - 4988.7 +1162.5 row 25 230 - 5058.7 +1162.5 row 24 231 - 5128.7 +1162.5 row 23 232 - 5198.7 +1162.5 dummy 233 - 5478.7 +1162.5 symbol pad coordinates (1) xy
2000 dec 07 52 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 note 1. all x/y coordinates represent the position of the centre of each pad (in m m) with respect to the centre (x/y = 0) of the chip (see fig.32). table 11 bonding pad dimensions dummy 234 - 5548.7 +1162.5 dummy 235 - 5618.7 +1162.5 alignment marks circle 1 - 5594.0 - 1162.5 circle 2 +5594.0 - 1162.5 circle 3 +5469.0 + 1162.5 circle 4 - 5369.0 + 1162.5 symbol pad coordinates (1) xy name dimension pad pitch 70 m m (minimum value) pad size, aluminium 62 100 m m passivation opening at pad 36 76 m m bump dimensions 52 90 17.5 m m wafer thickness (excluding bumps) 381 m m
2000 dec 07 53 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... handbook, full pagewidth mgt139 pad149 pad 1 row 34 row 55 row 22 row 0 col 25 col 50 col 75 v ss2 v ss1 v dd2 v lcdout v lcdsense v dd1 v lcdin v 2 v 3 v 4 v 5 v dd3 pc8820-1 pad 235 circle 4 (1) circle 1 (1) circle 2 (1) t2 t6 t5 osc t4 t3 t1 sa1 sa0 sda_out scl sda_in row 23 row 33 . . . . . . circle 3 (1) pad 150 row 66 row 56 . . . . . . . . . col 0 . . . col 100 . . . . . . . . . . . . 2.59 mm res 11.46 mm x y 0, 0 fig.32 bonding pad locations. (1) circles 1 to 4 are alignment marks with a diameter of 100 m m.
2000 dec 07 54 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 15 device protection circuits symbol pad remark internal circuit v dd1 179 to 184 note 1 v dd2 188 to 194 note 1 v dd3 185 to 187 note 1 v ss1 206 to 211 note 1 v ss2 198 to 203 note 1 v lcdin 166 to 171 note 1 v lcdsense 172 v lcdout 173 to 178 note 1 v 2 162 v 3 163 v 4 164 v 5 165 mgu179 v ss1 mgu180 v ss1 v ss2 mgu179 v ss1 mgu181 v ss1 v ss2 mgu179 v ss1 mgu182 v ss1 v lcdin
2000 dec 07 55 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 note 1. internally shorted via metal. sa0 204 sa1 214 t1 205 t2 221 t3 212 t4 213 t5 217 t6 218 osc 220 res 219 scl 215 and 216 note 1 sda_in 195 and 196 note 1 sda_out 197 r0 to r22 (block 1) 3 to 25 r23 to r33 (block 2) 232 to 222 r34 to r55 (block 3) 148 to 127 r56 to r66 (block 4) 151 to 161 c0 to c24 (block 5) 26 to 50 c25 to c49 (block 6) 51 to 75 c50 to c74 (block 7) 76 to 100 c75 to c100 (block 8) 101 to 126 symbol pad remark internal circuit mgu183 v ss1 v dd1 mgu179 v ss1 mgu184 v lcdin 1 diode per block v ss1
2000 dec 07 56 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 16 tray information handbook, full pagewidth mgt141 d c a x y f e b fig.33 tray details. for the dimensions of a to f: see table 12. table 12 tray dimensions handbook, halfpage mgt142 pc8820-1 fig.34 tray alignment. the orientation of the ic in a pocket is indicated by the position of the ic type name on the die surface with respect to the chamfer on the upper left corner of the tray. refer to fig.32 for the orientation and position of the type name on the die surface. dimension description value a pocket pitch in x direction 13.77 mm b pocket pitch in y direction 4.45 mm c pocket width in x direction 11.61 mm d pocket width in y direction 2.75 mm e tray width in x direction 50.8 mm f tray width in y direction 50.8 mm - no. pockets in x direction 3 - no. pockets in y direction 10
2000 dec 07 57 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 17 data sheet status note 1. please consult the most recently issued data sheet before initiating or completing a design. data sheet status product status definitions (1) objective speci?cation development this data sheet contains the design target or goal speci?cations for product development. speci?cation may change in any manner without notice. preliminary speci?cation quali?cation this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. product speci?cation production this data sheet contains ?nal speci?cations. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. 18 definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19 disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 20 bare die disclaimer all die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of philips' delivery. if there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. there are no post packing tests performed on individual die or wafer. philips semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. accordingly, philips semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. it is the responsibility of the customer to test and qualify their application in which the die is used.
2000 dec 07 58 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 21 purchase of philips i 2 c components purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
2000 dec 07 59 philips semiconductors product speci?cation 67 101 grey-scale/ecb colour dot matrix lcd driver pcf8820 notes
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